Archive for September 2014
Memory
Model –
Von Neumann
Architecture
Fetches instructions
and data from a single memory space- # Also known as Princeton architecture
Limits operating
bandwidth
CISC designs are also
more likely to feature this model
Uses unified cache
memory: instructions and data may be stored in the same cache memory
Can be either reading
an instruction or reading/writing data from/to the memory- # Both cannot occur at the same time since the instructions and data use the same bus system.
Memory Model –
(Pure or Strict) Harvard Architecture
The original
Harvard architecture computer,the Harvard Mark I, employed entirely separate
memory systems to store instructions and data. Uses two separate memory spaces for program
instructions and data – separate pathways with separate address
spaces- # Allows for different bus widths
- # Improved operating throughput
RISC designs are also more likely to feature
this model Note that having separate address spaces can
create issues for high-level programming no supporting different
address spaces (not good for CISC!) The CPU can both read an instruction and
perform a data memory access at the same time, even without a cache- #Faster (than Von Neumann) for a given circuit complexity because instruction fetches and data access do not contend for a single memory pathway.
Example: PIC Microcontrollers (Separate
code and data spaces)
Memory Model –
(Modified or
Non-Strict) Harvard architecture
A Modified Harvard architecture
machine is very much like a Harvard architecture
machine
Modification can be different- The program and data memory occupy different address spaces, but there are operations to read and/or write program memory as data.
- It relaxes the strict separation between memories while still letting the CPU concurrently access two (or more) memory busses
- #It offers separate pathways with the unified address spaces of the memory
- #As far as the programmer is concerned the machine performs like a von Neumann machine
Remember: many modern computers
that are documented as Harvard Architecture
are, in fact, Modified Harvard Architecture Applications- # Atmel AVR 8-bit RISC microcontroller
- #PlayStation Portable's WLAN chip, and many more; anything with enhanced DSP application; x86 (Intel) processors, ARM cores (ARM9) embedded as applications processors in cell phones, and PowerPC.
RISC vs. CISC
Complex Instruction Set Computers
(CISC)
·
In the 70s, advances took place in
the semiconductor industry
·
No revolutionary architecture or organization improvement
·
The trend was to increase the
microcode complexity,
leading to Complex Instruction
Set Computers (CISCs).
·
Each instruction performing a
complex sequence of
operations over many cycles.
Complex Instruction
Set Computer (CISC)- #Many addressing modes and long instructions
- #High code density
- #Often require manual optimization of assembly code for embedded systems
Reduced Instruction Set Computers (RISC)- # Original concepts emerged from optimizing compiler
- >Powerful, complex instructions are hard to use
- > Compiler-generated code makes frequent use of a relatively small number of simple instructions.
- #Emerged from the universities and research labs:
- > IBM 801 Computer [John Cocke 1975]
- > Berkeley RISC [David Patterson 1980] _ Sun SPARC
- > Stanford MIPS [John Hennessy] _ MIPS
- #RISC Features
- Architectural
- o Fixed instruction size with few formats
- o Load-store architecture
- o Smaller die size
- Performance
- o Pipelined execution
- o Single cycle execution
- o Higher clock rate
- Drawbacks
- o Poor code density, compared with CISC
- o Increased power consumption
Reduced Instruction
Set Computer (RISC)
Compact, uniform instructions = facilitate pipelining
More lines of code = large memory footprint
Allow effective compiler optimization
Microprosessors
